About the role
About FuriosaAI
FuriosaAI builds high-performance, high-efficiency AI compute for the Inference Era. Founded in 2017 by veteran semiconductor and AI algorithm engineers, Furiosa operates globally with offices in Korea and Silicon Valley, along with a compiler-focused R&D lab in Lisbon.
Our vision is to make AI computing sustainable, enabling access to powerful AI for everyone on Earth. We solve the AI hardware energy and operational cost crisis at the architectural level, rather than through brute force, building the world's first truly AI-native compute platform to unlock the full potential of artificial intelligence for every enterprise.
Key Responsibilities
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Define and implement block/IP/SoC verification plans, build verification test benches to enable block/IP/sub-system/SoC level verification
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Develop functional tests based on verification test plan
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Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
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Debug, root-cause and resolve functional failures in the design, partnering with the Design team
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Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
Minimum Qualifications
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Bachelor's degree in Electrical Engineering, Computer Science or other technically related fields
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3+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog/UVM based methodologies
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Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
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Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Preferred Qualifications
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Master’s degree in Electrical Engineering, Computer Science or other technically related fields.
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Experience in development of UVM based verification environments from scratch
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Experience with IP or integration verification of high-speed interfaces like PCIe, UCIe, DDR
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Experience with verification of ARM/RISC-V based sub-systems or SoCs
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Experience with Chisel is a plus
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Strong Python programming skills
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Good communication skills
Why Join FuriosaAI
The defining bottleneck of the AI era is building the right hardware and software stack to run it at global scale. Furiosa is solving this challenge holistically from the ground up.
With our flagship chip, RNGD, in mass production today and our next-generation platform in development with Broadcom, we are proving that full-stack, tensor-native compute is the future of AI infrastructure. This is a pivotal moment to join our team, right as we accelerate our global expansion.
At Furiosa, you will:
Solve AI’s Most Urgent Challenge. Help build the high-performance, energy-efficient inference hardware and software required to fulfill the promise of advanced AI.
Pioneer Full-Stack Co-Design. Work with teams that are architecting solutions from silicon up through the compiler (featuring innovations like Tensor Contraction Language and Virtual ISA) and serving frameworks.
Ship Real-World Silicon, Software, and Solutions. Turn breakthrough technology into commercial deployment. RNGD is in mass production with TSMC and running live enterprise workloads for global leaders like LG AI Research and Samsung SDS.
Partner With the Industry's Best. Collaborate across an elite global ecosystem that includes TSMC, Broadcom, SK Hynix, and GUC.
Do Your Life’s Best Work. Join a brilliant, low-ego, mission-driven team in a high-trust environment that values autonomy, intellectual curiosity, and shared ambition.
Contact
• talent@furiosa.ai