DV - Principal Digital Verification Engineer

Join the leading chiplet startup!  As an Eliyan Principal Digital Verification Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility.  You will be a key technical leader in developing state-of-the-art testbenches and unit/chip level test cases for best-in-class PHYs and Controllers. You will lead verification methodologies for Eliyan products.  You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products.  We offer a fun work environment with excellent benefits. Key Responsibilities: • Provide technical verification leadership to Eliyan products and provide guidance to junior engineers. • Develop and execute verification plans for connectivity IPs and Chiplets . • Create and maintain SystemVerilog/UVM-based verification environments . • Write and debug SystemVerilog/UVM compliant test cases for block and chip level. • Maintain a regression environment for enabling design CI/CD pipelines. • Collaborate with design engineers to ensure design quality with continuous micro-architecture, test-plan, and coverage reviews. • Develop, maintain, and track various test plan items and progress towards RTL freeze. • Stay up to date with industry trends, emerging technologies and progress in standards’ bodies. • Ensure IP compliance with industry standard protocols. • Integration of 3rd party VIPs and coordinate feature/bug tracking requests. • Perform in the capacity of a technical leader for junior verification engineers. • Create, improve, maintain DPI based FW simulation environments. • Create, improve, maintain gate level simulation environments for functional and power simulations. • Drive state of art verification methodologies for silicon verification including constrained based random verification, coverage driven verification. • Create microcontroller sub system testbenches and verification plan. • Own end-to-end verification for the company products. • Automation of verification flows including automated regression flow Qualifications: • BS in Electrical Engineering and related fields with 15+ years of experience • Strong expertise in UVM, test environment and assertion coding with SystemVerilog • Strong expertise on coverage driven verification • Proficiency in 3rd party tools for regression management and coverage analysis • Experience working on connectivity interfaces and protocols. • Knowledge of IO interface is a plus • Strong bias for innovations across all aspects of digital verification including automation of mundane activities and methods for quality improvement • Experience in verifying 3rd party mixed signal IPs as well as integration of VIPs • Proven track record of being part of a start-up like environment • Strong debugging skills • Strong understanding of microcontroller architecture and related peripheral talking to microcontrollers • Hands on experience with one of the scripting languages